Q47,Paper 2,D13. The virtual address generated by a CPU is 32 bits. The Translation Look-aside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4-cache lines in the set). The page size is 4 KB. The minimum size of TLB tag is

(A) 12 bits

(B) 15 bits

(C) 16 bits

(D) 20 bits

Answer c.

Explanation: Size of a page = 4KB = 2¹²
Total number of bits needed to address a page frame  is 32 – 12 = 20
If there are ‘n’ cache lines in a set, the cache placement is called n-way set associative. Since TLB is 4 way set associative and can hold total 64 (2^6) page table entries, number of sets in cache = 2⁶/4 = 2⁴. So 4 bits are needed to address a set, and 16 (20 – 4) bits are needed for tag.